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[VHDL-FPGA-Verilog] Verilog_UDP

Description: 辛辛苦苦找到的UDP的资料，在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段，在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西，希望能帮助大家解决“用户原语”相关的问题。-UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.
Platform: | Size: 125952 | Author: 龙也 | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[Post-TeleCom sofeware systems] qam_64

Description: 64QAM调制,采用硬件语言verilog实现,其中调用了DDS的IP核-64QAM modulation, using language verilog hardware implementation, which is called the IP core of the DDS
Platform: | Size: 1024 | Author: zhujing | Hits:

[Other] altera_nand_controller

Description: Altera合作伙伴Eureka Technology.和Cast Inc.为Altera FPGA芯片定制的Nand flash controller IP core-Altera partner Eureka Technology. And the Cast Inc. For the Altera FPGA chip custom Nand flash controller IP core
Platform: | Size: 296960 | Author: Trevor | Hits:

[VHDL-FPGA-Verilog] Ipcoredesign

Description: 微电子/软硬IP核设计：IP核脚本指南，模型开发指南-Microelectronics/soft and hard IP core design: IP core Scripting Guide, Model Development Guide
Platform: | Size: 581632 | Author: qq | Hits:

[VHDL-FPGA-Verilog] fsk

Description: 用Verilog实现FSK调制，调用IP核实现正弦余弦的调制-Verilog implementation using FSK modulation, called IP core to achieve the modulation sine cosine
Platform: | Size: 1024 | Author: Sapphire | Hits:

[VHDL-FPGA-Verilog] xapp655

Description: xapp655 from xilinx website: Mixed-Version IP Router (MIR) in Verilog
Platform: | Size: 54272 | Author: bugidan | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7verilog

Description: ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Platform: | Size: 1400832 | Author: zdh | Hits:

[VHDL-FPGA-Verilog] CANProtocolControllerIPCoreinVerilog

Description: 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
Platform: | Size: 67584 | Author: Nicholas | Hits:

[VHDL-FPGA-Verilog] xge_mac

Description: 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below. . |-- doc - Documentation files | |-- rtl | |-- include - Verilog defines and utils | `-- verilog - Verilog source files for xge_mac | |-- sim | |-- systemc - SystemC simulation directory | `-- verilog - Verilog simulation directory | `-- tbench |-- systemc - SystemC test-bench source files `-- verilog - Verilog test-bench source files ------------------------ 2. Simulation ------------------------ There are two simulation environments that can be used to validate the code. The verilog simulation is very basic and meant for those who want to look at how the MAC operates without going through the effort of setting up SystemC. The SystemC environment is more sophisticated and covers
Platform: | Size: 899072 | Author: xuchao | Hits:

[Embeded-SCM Develop] ARMcore

Description: 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
Platform: | Size: 690176 | Author: 王钊 | Hits:

[VHDL-FPGA-Verilog] sd_slave_device

Description: verilog source code for SD card SLAVE DEVICE IP-Core
Platform: | Size: 15360 | Author: Antti Lukats | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
Platform: | Size: 896000 | Author: panzhijian | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] TERASIC_AUDIO

Description: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Platform: | Size: 125952 | Author: changjiang | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Platform: | Size: 3072 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[VHDL-FPGA-Verilog] IIC

Description: 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
Platform: | Size: 3072 | Author: 吴梁辛 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:
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